1. Field of the Invention
The invention relates to phase-locked loop ("PLL"), and more particularly to phase-locked loops well suite for use as clock synthesizers.
2. Background of the Invention
Frequency synthesizers are widely used as frequency multipliers wherein one or more output signals are generated from a single input signal. The input signal oscillates at one frequency, while the output signals oscillate at some number N times the input signal frequency. Frequency synthesizers are used in numerous applications, including, but not limited to clock generation and clock distribution in personal computer systems. These frequency synthesizers (or, as they are sometimes called, clock generators or synthesizers) are often used in an environment with a poorly regulated power supply. Often, the negative impact on the performance of a frequency synthesizer caused by the power supply is further aggravated by the effects of certain switching logic circuits.
An example of a conventional PLL is shown in FIG. 1. The input signal 1 (referred to herein as a "predecessor signal") enters the PLL 2 and is optionally modified by a frequency divider 3 to produce an "input signal" 11. In the prior art circuit, the input signal can also be referred to as a "reference signal". The reference signal is then compared in a phase detector 4 with the output signal 9 as modified by a second frequency divider 8. The relative difference in phase or "phase error" between these two signals is represented by a frequency adjustment signal on the output of the phase detector 4. The output of the phase detector is provided to a charge pump 5 and is then filtered in a low-pass filter 6 to eliminate the unwanted higher frequency components of the signal produced by the phase detector 4. The resulting output frequency control signal controls a voltage-controlled oscillator ("VCO") 7 which produces the output signal 9. The output signal 9 has a frequency f.sub.out which is proportional to the voltage of the signal produced by the low-pass filter 6. As described above, the output signal 9 is fed back to the phase detector 4 via a frequency divider 8.
An important effect of modifying the output frequency in response to the phase error is that the output signal, while having a frequency that is a multiple of the frequency of the input signal, can remain at a constant phase shift from the input signal. The output signal of a properly functioning PLL is thus "locked" on the input signal and the loop is said to be phase locked.
The output frequency produced by a PLL is related to the input signal frequency by the formula EQU f.sub.out =N/D.times.f.sub.pr
where N is the factor by which the output frequency is divided in the frequency divider 8 and D is the factor by which the input frequency is divided in the frequency divider 3. When the loop is phase-locked, the phase detector operates at a frequency equal to f.sub.out /N which is also equal to f.sub.pr /D.
In many frequency synthesizers, the divisor N can be a large number. But because the output signal frequency is divided by N before being provided to the phase detector, the output signal frequency can only be sampled every N cycles of the output signal. Thus the generation of the phase error signal by the phase detector 4, and the adjustment of the output signal, can only occur every N cycles of the output signal (or equivalently, only once for each (relatively long) cycle of the input signal). The VCO is essentially operating "open loop" in-between the correction events. If N is sufficiently large and the input signal has a certain level of noise, the output signal may unacceptably "drift" and unlock from the input signal. In some cases the output signal may fail to lock onto the input signal at all.
The PLL may also produce what is known as "jitter" (limited but persistent back-and-forth variations in the output signal frequency). Any disturbance, noise from the power supply, for example, interferes with the VCO and may cause excessive jitter. A noise transient cannot be corrected until the next correction cycle which can be as far as N output cycles away.